library verilog;
use verilog.vl_types.all;
entity zl_2346_3_vlg_sample_tst is
    port(
        clk             : in     vl_logic;
        datain          : in     vl_logic_vector(7 downto 0);
        en1             : in     vl_logic;
        en2             : in     vl_logic;
        sampler_tx      : out    vl_logic
    );
end zl_2346_3_vlg_sample_tst;
